1. Field of the Invention
The present invention relates to a complementary metal-oxide semiconductor integrated circuit of a master slice type and, more particularly, relates to an arrangement of internal functional gate devices therein.
Master slice type of integrated circuits are classified into a metal-oxide semiconductor type and a bipolar type based on kinds of semiconductors constituting the integrated circuits. From a viewpoint of achieving high integration, a metal-oxide semiconductor type is generally superior to a bipolar type. Further, of metal-oxide semiconductor types, a complementary metal-oxide semiconductor type has an advantage that power to be consumed at the time of high integration is relatively small. Therefore, a complementary metal-oxide semiconductor type tends to be largely used in a master slice type of integrated circuit.
FIG. 1 schematically shows a general chip arrangement of a complementary metal-oxide semiconductor integrated circuit of a master slice type. A rectangular chip 15 comprises in its periphery four peripheral blocks 11, 12, 13 and 14. In the inner regions surrounded by these peripheral blocks, for example, four internal functional gate regions 21, 22, 23 and 24 are disposed, respectively, spaced apart from one another. Regions between the respective internal functional gate regions become wiring zones 31, 32 and 33.
The peripheral blocks are blocks for inputs/outputs interface. In the block, for example, a conversion of signal levels is made. In the internal functional gate regions, circuit elements such as transistors and the like are regularly arrayed. Various kinds of logical gates are structured by properly wiring these circuit elements. Inputs and outputs of the logical gate thus structured are properly connected through wiring in the wiring zones. In such a way, a circuit for achieving a specific operation is made.
FIG. 2 shows in detail an enlarged internal functional gate region 22 as shown in FIG. 1. Referring to FIG. 2, the internal functional gate region and wiring zones will be described in detail. Wiring zones 31 and 32 are formed on both sides of the internal functional gate regions 22. In a portion 10' of the internal functional gate region 22, a logical gate (for example a NOR gate having three inputs) is structured. Four input and output terminals of the logical gate are connected to longitudinal wirings 41, 42, 43 and 44, respectively, within the wiring zone 31. In the wiring zone, lateral wirings (not shown) further exist, other than the longitudinal wirings as shown. However, in general, a longitudinal wiring is used for connecting input/output terminal of a logical gate structured in an internal functional gate region. A position or location where a longitudinal wiring is provided in a wiring zone is predetermined, which is called a longitudinal lattice. In FIG. 2, dotted lines 100 and 90 indicate a longitudinal lattice. For the purpose of simplicity of formation, it is usual that each distance between longitudinal lattices is constant, as shown.
An arrangement of an internal functional gate region in a complementary metal-oxide semiconductor integrated circuit of a master slice type of interest to the present invention is shown in M. Asheda, et al, "A3000-Gate CMOS master slice LSI". Procedings of the 11th Conference on Solid State Device, Tokyo PP. 204-206, 1979. The internal functional gate region in the prior art includes an arrangement as shown schematically in FIG. 3 which is a plan view. In addition, cross sectional views taken in VI--VI line to VIII--VIII line in FIG. 3 are shown, respectively, in FIGS. 4 to 8.
It can be seen that four complementary metal-oxide semiconductors are formed in the internal functional gate region 22 in FIG. 3. Four pairs, each pair comprising a structure including a P-channel metal-oxide semiconductor and an N-channel metal-oxide semiconductor, which structure forms a complementary metal-oxide semiconductor, includes common gates 41, 42, 43 and 44, respectively. Each P-channel type of metal-oxide semiconductor is formed in the upper region in the internal functional gate region 22 (corresponding to the cross section VII--VII). Similarly, each N-channel type of metal-oxide type semiconductor is formed in a lower portion or region of the internal functional gate region 22 (corresponding to the cross section VIII--VIII). The regions 61 and 62 in the upper portion of the internal gate region 22 are source-drain regions of the P-channel metal-oxide semiconductor. The regions 81 and 82 in the lower portion of the internal functional gate region 22 are a source-drain region of the N-channel metal-oxide semiconductor.
Four complementary metal-oxide semiconductors thus structured are divided into two basic cells, that is, basic repetition units. One basic cell comprises a complementary metal-oxide semiconductor having a gate 41 and a complementary metal-oxide semiconductor having a gate 42, and the other basic cell comprises a complementary metal-oxide semiconductor having a gate 43 and a complementary metal-oxide semiconductor having a gate 44. An electrical isolation region and substrate connecting regions 52 and 72 for making an electrical contact with a substrate are provided between two basic cells. In FIG. 3, such electrical isolation region includes all of the regions in the internal functional gate region 22 except for a gate region, source-drain region and substrate connecting regions. Regions 51, 53, 71 and 73 are substrate connecting regions provided between a basic cell as not shown and a basic cell as shown herein.
FIG. 4 is a cross sectional view showing a cross section IV--IV in FIG. 3. A gate 41 is provided on an isolation region 201 for electrically isolating each device. A source-drain diffusion region 61 in a P-channel metal-oxide semiconductor and a source-drain diffusion region 81 in an N-channel metal-oxide semiconductor are provided between isolation regions. A P-type silicon substrate 203 plays a role of a substrate for an N-channel metal-oxide semiconductor. An N-type well diffusion region 202 formed within a P-type silicon substrate 203 plays a role of a substrate for a P-channel metal-oxide semiconductor.
FIG. 5 is a cross sectional view showing a cross section V--V in FIG. 3. The cross sectional view is the same as the cross sectional view of FIG. 4 excluding gate 41.
FIG. 6 is a cross sectional view showing a cross section VI--VI in FIG. 3. In this cross section, substrate connecting regions 52 and 72 are formed between each isolation region 201. The remaining portions are the same as the cross sectional view FIG. 5.
FIG. 7 is a cross sectional view showing a cross section VII--VII in FIG. 3. An N-type well diffusion region 202 formed in a P-type silicon substrate 203 is a substrate for a P-channel type of metal-oxide semiconductor. In FIG. 7, four P-channel type metal-oxide semiconductors are formed. For example, a P-channel metal-oxide semiconductor having a gate 41 is structured by a gate oxide film 204 formed on the substrate 202, a gate 41 formed on the gate oxide film 204 and two source-drain regions 61 formed in the substrate 202 on both sides of the gate region. Further three P-channel metal-oxide semiconductors are structured by the same manner. These four metal-oxide semiconductors are divided into two basic cells by the substrate connecting region 52 and the electric isolation region 201.
FIG. 8 is a cross sectional view showing a cross section VIII--VIII in FIG. 3. In this cross section, four N-channel metal-oxide semiconductors are provided, which become complementary to four P-channel metal-oxide semiconductors provided in FIG. 7.
Returning to FIG. 3, there are a plurality of longitudinal lattices in the wiring zones 31 and 32, as shown in dotted lines. The longitudinal lattices are provided equidistantly to correspond to gate, source, drain regions in the internal functional gate region 22.
Now, referring to FIG. 9, a wiring arrangment is illustrated where a logical gate is structured in the internal functional gate region as shown in FIG. 3. In this example, a three-input NOR gate comprising three input terminals 111, 112 and 113 and an output terminal 114, as shown in FIG. 10, is structured. Solid lines 111-118 indicate wirings. Solid points in the wiring mean that the wirings are electrically connected to a region thereunder. Wirings 111-114 in the wiring zone 31 are longitudinal wiring for connecting inputs and output of the three-input NOR gate shown by FIG. 10, which are denoted in the same reference numerals as those of the wirings 111-114. These longitudinal wirings are disposed on the longitudinal lattices as shown in dotted lines.
A three-input NOR gate comprises four terminals. Thus, only four longitudinal lattices are needed for longitudinal wiring. However, the three-input NOR gate as structured herein spans five longitudinal lattices 102-106. The reason is that the longitudinal lattice 105 is not effectively utilized. The longitudinal lattice 105 corresponds to an isolation region (and a substrate connecting region) between basic cells. Accordingly, the longitudinal lattice 105 can never be used as a longitudinal wiring for input and output of the logical gate.
Furthermore, the three-input NOR gate is structured by three metal-oxide semiconductors. Thus, there is one metal-oxide semiconductor too many in one basic cell. However, since this metal-oxide semiconductor is not electrically isolated from another metal-oxide semiconductor in the same basic cell, it can not be utilized for constituting other logical gate.
Thus, according to the internal functional gate region of the prior art, an internal functional gate region corresponding to the longitudinal lattices 102-108 was needed for constituting a three-inputs NOR gate. However, the region effectively utilized is merely a region corresponding to the longitudinal lattices 102, 103, 104 and 106. The internal functional gate region of a conventional complementary metal-oxide semiconductor master slice integrated circuit comprises basic cells each comprising more than one complementary metal-oxide semiconductors and isolation regions for electrically isolating between each basic cell. Therefore, the above described problems necessarily arise. This is a big obstacle for high integration of integrated circuit.